We provide services in the following areas:

• Architecture definition
• Methodology and Tools Setup
• Verification Plan development and Verification Environment Setup
• RTL coding in Verilog/ VHDL
• Deterministic, Random and Regression Tests
• Scan insertion and Design for Testability
• Synthesis and netlist generation
• Gate level simulation
• Optimization
• Static Timing Analysis and timing extraction
• ATPG/ test vector generation
• Formal Verification